1. Field of the Invention
The present invention relates to stacks in which a plurality of integrated circuit (IC) packages arranged in a stack are electrically connected in a desired fashion, and to methods of making such stacks.
2. History of the Prior Art
Various common approaches are used to increase memory capacity on a circuit board. Larger memory IC devices such as chips can be used, if available. The size of the circuit board can be increased in order to hold more IC chips. Vertical plug-in boards can be used to increase the height of the mother board. The memory devices can be stacked in pancake style (sometimes referred to as 3D packaging or Z-Stacking). The Z-Stacking approach interconnects from 2 to as many as 8 chips in a single component which can be mounted on the xe2x80x9cfootprintxe2x80x9d of a single package device. This approach is the most volumetrically efficient. Package chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form have been used for stacking, and are perhaps the easiest to use. Bare chips or dies have also been used, but the process for forming a stack thereof tends to be complex and not well adapted to automation.
In forming a stack of IC chips such as memory chips, the chips must be formed into a stack and at the same time must be electrically interconnected in the desired fashion. Typically, the chips, which are mounted within packages therefor, have most of the electrical contacts thereof coupled in common or in parallel to contacts on a supporting substrate, and several unique contacts which are coupled individually to the substrate to the exclusion of the other chips. The prior art includes various different arrangements for electrically interconnecting the IC chips in a stack. For example, electrical conductors which may comprise thin film metal on an insulating base may be disposed perpendicular to the planes of the planar chips so as to connect those conductors on each chip which are exposed through openings in an insulating layer. Where the chip packages are assembled into a stack, electrical connections may be accomplished by lead frames or solder strips extending along the sides of the stack and attached to the electrical contacts of the chips.
Another common technique for providing the desired electrical interconnections in a chip stack is to form a stack of chips having bonding pads disposed on the chips adjacent the outer edges thereof. After assembling the stack of chips, the chip edges are ground flat and polished before sputtering an insulating layer thereon. The bonding pads on the edges of the chips are masked during the sputtering process to avoid covering them with the insulating layer. Next, a metal layer is sputtered onto the entire edge of the stack in conjunction with photomasking which forms conductive traces of the metal layer in desired locations for connecting the bonding pads.
Further examples of vertical stacks of IC chips and various methods of making such stacks are provided by U.S. Pat. Nos. 4,956,694, 5,313,096 and 5,612,570, which patents are commonly assigned with the present application. U.S. Pat. No. 5,612,570, which issued Mar. 18, 1997 and is entitled CHIP STACK AND METHOD OF MAKING THE SAME, describes a chip stack and a method for making the same in which chip packages are first assembled by mounting plastic packaged chips or thin, small outline package chips (TSOPs) within the central apertures of thin, planar frames having a thickness similar to the thickness of the packaged chip. Leads at opposite ends of the package are soldered to conductive pads on the upper surface of the surrounding frame. Each frame also has other conductive pads on the upper and lower surface thereof adjacent the outer edges of the frame, which are coupled to the conductive pads that receive the leads of the packaged chip by conductive traces and vias. A chip stack is then formed by stacking together a plurality of the chip packages and dipping the upper edges of the stack into molten solder to solder together the conductive pads adjacent the outer edges of the frames. The conductive pads adjacent the outer edges of the frame can be interconnected in a stair step arrangement, and pads on opposite sides of each frame can be coupled in offset fashion using vias, in order to achieve desired electrical interconnections of the various chips.
A still further example is provided by copending application Ser. No. 08/935,216, filed Sep. 22, 1987 and entitled CHIP STACK AND METHOD OF MAKING SAME. Such application, which is commonly assigned with the present application, describes formation of a stack of ball grid array IC packages by assembling a ribbon-like structure of thin, planar bases, each with plural terminals and an interconnecting conductive pattern thereon, and with the bases electrically interconnected by flex circuits extending therebetween. A different IC package is mounted on each base by soldering the balls of a ball grid array thereon to the terminals of the base. The bases alternate in orientation, so that alternate IC packages are joined to the tops and bottoms of the bases. The resulting arrangement is then folded over on itself, with IC packages being joined to adjacent bases using adhesive. The resulting chip stack is mounted on a substrate by soldering the balls of the ball grid array at the underside of the lowermost base at the bottom of the stack to the substrate. The conductive patterns on the bases and the interconnecting flex circuits form conductive pads which contact selected terminals of the various IC packages as the pads extend in alternating fashion through the stack between opposite sides of the stack.
A still further example is provided by copending application Ser. No. 08/971,499, filed Nov. 17, 1997 and entitled METHOD OF MAKING CHIP STACKS. Such application, which is commonly assigned with the present application, describes the making of a chip stack which begins with the formation of a plurality of panels having apertures therein and conductive pads on opposite sides thereof. Solder paste is deposited on the conductive pads prior to mounting plastic packaged IC chips within each of the apertures in each of the panels so that opposite leads thereof reside on the conductive pads at opposite sides of the apertures. The plural panels are then assembled into a stack, such as by use of a tooling jig which aligns the various panels and holds them together in compressed fashion. The assembled panel stack is heated so that the conductive paste solders the leads of the packaged chips to the conductive pads and interfacing conductive pads of adjacent panels together, to form a panel stack comprised of a plurality of chip package stacks. Following cleaning of the panel stack to remove solder flux residue, the individual chip package stacks are separated from the panel stack by cutting and breaking the stack. Score lines across the topmost panel and transverse slots within remaining panels therebelow result in the formation of strips of chip package stacks when longitudinal cuts are made through the panel stack. The remaining portions of the uppermost panel within such strips are then snapped along the score lines thereof to separate the individual chip package stacks from the strips.
A still further example is provided by copending application Ser. No. 09/073,254, filed May 5, 1998 and entitled CHIP STACK AND METHOD OF MAKING SAME. Such application, which is commonly assigned with the present application, describes a stackable carrier made from plural layers of Kapton or other plastic material, and which may be made using conventional flex circuit techniques. The stackable carrier has a central opening, a plurality of stacking apertures extending through the thickness thereof between opposite surfaces of the carrier and a conductive pattern therein which extends between the central opening and the stacking apertures. An IC device is mounted within the central opening, and is electrically coupled to the conductive pattern such as by wire bonding or by soldering a ball grid array or other arrangement of contacts on the device directly to the conductive pattern, and is encapsulated therein with potting compound using conventional chip-on-board encapsulation technology, to form a single layer integrated circuit element. Conductive elements such as metallic balls are inserted into the stacking apertures, and are mounted therein using solder or conductive epoxy, so as to electrically contact the conductive pattern and form a stackable IC package. A stack of the IC packages is assembled by arranging a stack of the packages so that the metallic balls which protrude from a surface of each package are inserted into the stacking apertures of an adjacent package, where they are electrically and mechanically secured by solder or conductive epoxy. Balls mounted within the stacking apertures of a lowermost one of the IC packages protrude from the bottom surface thereof, so that the completed stack forms a ball grid array product.
The various arrangements and methods described in the patents and patent applications noted above have been found to provide IC package stacks and methods which are advantageous and which are suited for many applications. Nevertheless, the provision of further alternative arrangements and methods would be advantageous. In particular, it would be advantageous to provide IC package stacks and methods of making such stacks which utilize available materials and known process techniques, including particularly flex circuit technology. The assembly of such stacks should lend itself to automated production methods, and thus be competitive with other stacking approaches.
The foregoing objects and features are achieved in accordance with the invention by an IC package stack and method of making the same which uses available materials and known process techniques and in which automated production methods can be used. A stackable flex circuit IC package in accordance with the invention includes an IC device and a flex circuit comprised of a flexible base with a conductive pattern disposed thereon. The IC device is mounted within a central aperture in a frame, and the flex circuit is wrapped around at least one end portion of the frame so as to expose the conductive pattern thereat. The IC device is electrically coupled to the conductive pattern. The conductive pattern of the flex circuit is comprised of a plurality of spaced-apart conductors. A stack of the stackable flex circuit IC packages may be formed, and the plurality of spaced-apart conductors of the flex circuits of adjacent IC packages are electrically coupled, such as by use of anisotropic conductive epoxy. By pressing the adjacent IC packages together, the conductive epoxy forms connections between the adjacent IC packages in a vertical or Z-axis direction while maintaining the spaced-apart conductors of the conductive pattern within each flex circuit electrically isolated from one another.
Where the IC devices comprise bare chips, the chip is electrically coupled to the conductive pattern of the flex circuit using wire bonds coupled between conductive pads of the chip and the conductive pattern of the flex circuit. A potting compound is applied to encapsulate the chip and the wire bonds within the frame. Alternatively, the IC devices may comprise BGA (Ball Grid Array) devices, such as chip scale packages, xcexcBGAs, flip chips, and the like, in which event an array of ball contacts or other conductive elements of the BGA device are disposed within apertures, formed such as by ablation, through the flexible base of the flex circuit. The balls of the grid pattern are soldered to the conductive pattern of the flex circuit to accomplish the electrical coupling. A potting compound is used to underfill a space between the surface of the chip having the ball grid array of contacts and the flexible base of the flex circuit.
Where the stackable flex circuit IC package has a bare chip mounted within a central aperture in the frame, the frame may be of elongated configuration with opposite ends of the flex circuit being mounted on the opposite step down ends of the frame so as to extend thereover and expose the conductive pattern at each of such opposite ends of the frame. Where a stack of the IC packages is assembled, a lowermost one of the packages in the stack may be provided with a plurality of contacts on the conductive pattern at each of the opposite ends to facilitate coupling and electrical interconnection of the stack to a substrate board. Within each IC package, the flex circuit extends across the central aperture in the frame, and the IC device is secured thereto within the aperture. Alternatively, in order to provide a thinner IC package, the flex circuit may be provided with a central aperture therein in the region of the central aperture in the frame. The IC device is disposed in the central aperture of the flex circuit so that a bottom surface of the IC device is generally coplanar with an adjacent lower surface of the flex circuit opposite the frame.
Where the IC package is formed using a BGA device, a central portion of the flex circuit has a plurality of holes ablated or otherwise formed therethrough in an array which corresponds with an array of conductive elements on the device. The conductive pattern is formed on the flex circuit so as to extend between the holes and four opposite edges of the flex circuit. After securing the frame to the flex circuit and the device to the flex circuit and mounting the device within the central aperture in the frame, the array of balls or other conductive elements at the bottom of the device are soldered to the conductive pattern on the flex circuit, with the balls disposed within the apertures in the flex circuit. The four opposite sides of the flex circuit are then wrapped over and bonded such as by adhesive to the frame, exposing the conductive pattern at the four edges of the frame. Upon stacking such IC packages, conductive epoxy such as anisotropic conductive epoxy is applied to the exposed conductive pattern at the four sides of the frame, and the application of pressure between adjacent IC packages completes the electrical interconnections between the individual conductors of the conductive pattern of adjacent IC packages.
A method of making a stackable flex circuit IC package in accordance with the invention includes the steps of providing a flex circuit with a conductive pattern thereon and providing a frame having an opening therein. The frame is secured onto the flex circuit so that the flex circuit is wrapped around at least one end of the frame to expose the conductive pattern at the at least one end. An IC device is secured to the flex circuit within the opening in the frame, and the device is electrically coupled to the conductive pattern on the flex circuit. The device is then encapsulated with epoxy. The flex circuit may be formed by sputtering or otherwise depositing a conductive layer on a layer of thin flexible base, followed by etching of the layer to form a desired conductive pattern. Where a bare chip is used, the electrical interconnection is accomplished by wire bonding the conductive pads of the chip to the conductive pattern of the flex circuit. In that event, the wire bonds are encapsulated as part of the step of encapsulating the chip with epoxy.
Where the IC package uses a BGA device, the step of providing a flex circuit includes forming a matrix of holes through the flexible base to the conductive pattern of the flex circuit. The ball grid array or other conductive elements of the device are disposed within the matrix of holes and coupled to the conductive pattern such as by soldering. A space between the circuit and the device is underfilled with epoxy. Thereafter, a frame having an opening therein is placed over the chip and is attached to the flex circuit, such as by adhesive. The opposite edges of the flex circuit are then folded over the frame and are bonded, again such as by adhesive.